FeMiPulse I

Pulse/delay programmer with a TCP/IP interface.

• 64k delays from 4 ns to 4 s, 4 ns step
• 14 outputs
• Built-in repetition loop with 64k counter
• 10 MHz clock input
• Built-in hardware timing protection circuitry
• Variety of front-ends

Overclocked (2.5 ns), extended memory (16M delays) and USB versions are available on request.

FeMiPulse II

FPGA-based pulse programmer with a TCP/IP interface.

• 16k delays with 4 ns–316 h duration
• 16 outputs
• 4 levels of nested cycles
• External trigger
• Zero service-time cycles, exact sequence
• Built-in protection circuitry and programmable clock output
• Variety of front-ends

FeMiLIN

10-channel multiharmonic lock-in amplifier with a TCP/IP interface.

• 1 MHz 16-bit input sampling
• 5 harmonics detection in IQ mode
• 10 harmonics detection in single mode
• Integrated ramp generator
• Integrated modulation DDS
• Continuous block streaming of acquired data

FeMiAWG

Arbitrary waveform generator and data acquisition module with a USB interface.

• 2 channels for IQ excitation
• 2 channels for IQ detection
• 50 MHz bandwidth
• 100 MS/s excitation and detection
• Sequence packaging
• Integrated phase cycling
• Loadable pulse shapes & sequences